The present invention relates, in general, to gallium arsenide based transistors, and more particularly, to Complementary Heterojunction Field Effect Transistors (CHFETs) having an anisotype N.sup.+ gate for P-channel devices.
Gallium arsenide based semiconductor complementary heterostructure devices have been predicted to offer significant speed and power advantage over silicon complementary devices, such as CMOS, under ideal conditions of insignificant leakage currents. A key to high speed, low power performance lies in realization of N-channel and P-channel FET devices having acceptable threshold voltages and low gate leakages and subthreshold currents. Several heterostructures have been reported in recent years which attempt to address these requirements. The speed/power performance of most devices is limited largely by gate leakage. Unlike silicon dioxide insulators of silicon based CMOS devices, the insulator layer in gallium arsenide HFET's, undoped aluminum gallium arsenide (AlGaAs) is not a true insulator, but is instead a semi-insulator with comparatively high leakage.
Of the CMOS like devices which can be realized using III-V materials, the simplest are the N and P-channel heterostructure insulated gate FETs (HIGFETs). These devices use a two-dimensional electron gas or hole gas for the N-channel and P-channel device, respectively for high mobility. In such HFETs with intentionally undoped structures, threshold voltages are essentially the difference in the metal semiconductor Schottky barriers and the conduction band or valence band discontinuities for the N-channel and P-channel devices, respectively. These threshold voltages are unfortunately not optimum for direct coupled FET logic applications. Threshold voltages are about 0.8 volt for N-channel and -0.7 volt for P-channel devices in such a structure. Since, in general, the gate turn on voltage occurs at gate voltages of 1.1 to 1.2 volts, these devices are limited in their voltage swing and hence speed/power performance.
Absolute value of threshold voltage can be adjusted to an appropriate range of 0.2 to 0.4 volts by using dopend channel or inverted pulse doped structures. For the N-channel device N.sup.+ indium gallium arsenide (InGaAs) or germanium gates have also been recently used to change barrier height of the N-channel device. This approach has been successfully applied to reduce threshold voltage of the N-channel HFET to the desirable range for direct coupled FET logic (DCFL) circuits. Threshold voltage of an N-channel HFET with an N.sup.+ InGaAs cap layer in the gate is the difference between InGaAs and GaAs work functions. Thus, the threshold voltage is set by the composition of the InGaAs cap. Even though the threshold voltage is reduced to appropriate range, improvement in gate leakage is needed. This requires enhancing barrier heights which control leakage.
One technique that has been used in the past in conjunction with N-channel field effect transistors is the use of an anisotype layer underneath the gate electrode, also called the gate metal. The anisotype layer either replaces or augments an existing Schottky junction between the gate conductor and the AlGaAs semi-insulating region which separates the gate conductor from the channel region. The effect of the anisotype layer is to increase the work function at the surface. Due to higher built-in potential, the gate turn-on voltage can be increased above that of a conventional N-channel FET. Similar principles, for example Shannon contacts, have been applied to silicon solar cell structures. Until now, however, this approach has not been applied to P-channel or complementary HIGFET structures.
Accordingly, it is an object of the present invention to provide a P-channel compound semiconductor based field effect transistor having lower gate leakage.
A further object of the present invention is to provide a complementary heterostructure field effect transistor structure having improved speed/power characteristics.
Still a further object of the present invention is to provide a complementary gallium arsenide based field effect transistor having improved P-channel device characteristics.